1. Field of the Invention
The present invention relates to processing devices capable of speculative execution of an instruction, and more particularly, to a processing device in which an executed result of an instruction becomes valid when all the predictions about true/false of one or more branch conditions are correct.
2. Description of the Background Art
FIG. 17 is a block diagram showing a structure of a microprocessor as a conventional instruction processor.
Referring to FIG. 17, the microprocessor includes a register file 1 formed of a plurality of registers, an Arithmetic and Logic Unit (hereinafter referred to as an ALU) 2 for performing an operation on data held in register file 1, a memory 3 for holding instructions as instruction codes, a program counter 4 for holding addresses for instructions to be executed and applying such an address to memory 3, and a circuit 5 for incrementing program counter 4.
The microprocessor further includes an instruction register 6 for holding an instruction code fetched from memory 3, an instruction decoder 7 for decoding the instruction code and generating a control signal for controlling reading/writing from/to register file 1 and a control signal for controlling ALU 2, a test circuit 8 for determining a branch condition based on data read out from register file 1, and a circuit 9 for calculating a target address in response to a control signal from test circuit 8.
Now, operations of the microprocessor will be described.
An instruction to be executed among instructions held in memory 3 is first addressed by program counter 4. The addressed instruction is fetched from memory 3 and held in instruction register 6. The instruction held in instruction register 6 is decoded by instruction decoder 7 and reading/writing from/to register file 1 is controlled and ALU 2 is controlled in response to the content of the instruction.
If the instruction fetched by instruction register 6 is an operation instruction, data is respectively read out from two registers in register file 1. These pieces of read out data are operated by ALU 2, and the resultant data is written in a register in register file 1.
Meanwhile, if an instruction fetched by instruction register 6 is a branch instruction, two pieces of data read out from register file 1 are applied to test circuit 8. Based on these pieces of data, test circuit 8 determines whether or not the branch condition is satisfied. More specifically, test circuit 8 determines whether the condition is true or false. If the condition is true, the target address is calculated by target address calculation circuit 9 and applied to program counter 4. If the condition is false, program counter 4 is incremented.
FIG. 5 is a flow chart showing an example of a program. According to the flow chart, instruction a1: r2=r0+r1 (more specifically, the values of registers r0 and r1 in register file 1 are added and stored in register r2 in register file 1) is executed in a basic block A. After condition a2: if (r2&lt;r3) is determined, either basic block B or E is initiated. More specifically, instruction b1: r4=r12+r13 in basic block B is to be executed when r2&lt;r3 is determined as false, and instruction e1 (not shown) in basic block E is to be executed when r2&lt;r3 is determined as true.
In accordance with the above-described conventional microprocessor, neither instruction b1 in block B nor instruction e1 in block E cannot be executed until condition a2 in block A is determined. For example, data resulting from execution of instruction b1 is written in a register r4 in register file 1 only when condition a2 in block A is false. To write data resulting from execution of instruction b1 in register r4 with condition a2 being true destroys data previously held by register r4.
Thus, the conventional microprocessor is not capable of executing instructions b1, c1 and d1 to be executed based on conditions a2 in block A, b2 in block B and c2 in block C shown in FIG. 5 until conditions a2, b2 and c2 are determined.
Although microprocessors having a plurality of ALU's have been proposed in recent years, such a microprocessor still cannot execute an instruction to be executed based on one or more conditions before determining these conditions. Since some of the plurality of ALU's are not operating at all for some moments, ALU's cannot be used efficiently, and sufficiently high speed operation processing cannot be achieved.